Printed circuit board with capacitors connected between ground layer and power layer patterns

ABSTRACT

A printed circuit board is disclosed. A top layer power supply pattern and a top layer ground pattern are formed. The top layer power supply pattern and the top layer ground pattern are connected to a power supply layer and a ground layer through a plurality of viaholes, respectively. A plurality of capacitors or a plurality of capacitor resistor series circuits are disposed at predetermined intervals between the top layer power supply pattern and the top layer ground pattern.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a laminated printed circuit board thathas at least two layers and that are used for electronic devices such asinformation processing devices and communicating devices, in particular,to a laminated printed circuit board having a function for suppressingan undesired electromagnetic wave from radiating.

2. Description of the Related Art

In advanced information society, undesired electromagnetic wavesradiated from electronic devices such as information processing devicesand communicating devices disturb broadcasting and radio communicationsystems and cause devices to malfunction. To suppress undesiredelectromagnetic waves from radiating and prevent them from entering suchdevices, shields and filters are used.

As a method for suppressing an undesired electromagnetic wave radiatedfrom an electronic device, an electromagnetic wave radiated from aprinted circuit board as a radiation source is enclosed with a shield.Alternatively, a printed circuit board is suppressed from radiating anelectromagnetic wave.

For example, in a printed circuit board disclosed as Japanese UtilityModel Registration Laid-Open Publication No. 05-13095, as shown in FIG.20, a ground layer of a printed circuit board 101 is electricallyconnected to a cage 107 through a leaf spring 102 and a metal guide rail103 so that the voltage of the ground layer is the same as the voltageof the cage 107. In this structure, the ground layer 104 functions as ametal plate so as to prevent electromagnetic noise from leaking out.

In an IC card disclosed as Japanese Patent Laid-Open Publication No.07-192105, as shown in FIG. 21, a printed circuit board 113 and a metalpanel 114 oppositely disposed with a frame 112 is electrically connectedwith a ground terminal 115 secured to the metal panel 114. Thus, themetal panel 114 effectively functions as a shield against externalelectrostatic induction and electromagnetic induction. Consequently, anIC chip 113 can be prevented from malfunctioning and breaking againstinterference of an undesired electromagnetic wave and radiation ofstatic electricity.

In a liquid crystal displaying device 120 disclosed as Japanese PatentLaid-Open Publication No. 06-82803, as shown in FIG. 22, a metal plate122 is electrically connected to a ground line of a printed circuitboard 121. Thus, a ground line voltage is stably supplied. In addition,a liquid crystal displaying screen 124 and a metal frame 123 function asshields for suppressing an undesired electromagnetic wave fromradiating.

As a main cause of which a printed circuit board radiates an undesiredelectromagnetic wave, a voltage between a ground for supplying areference voltage and a power supply layer for supplying a power supplyvoltage to an IC and so forth fluctuates. In particular, when a systemcomposed of a power supply layer and a ground layer resonates, anelectromagnetic wave in very high level is radiated. To suppress aradiation due to the fluctuation of a power supply voltage, severalstructures of printed circuit boards have been proposed.

In a printed circuit board disclosed as Japanese Patent Laid-OpenPublication No. 06-224562, as shown in FIG. 23, a part 131 of a powersupply plane layer 133 is separated. The separated power supply planelayer 131 is disposed on a substrate 134 that is disposed adjacent to aground plane layer 132. The power supply plane layer 131 separated fromthe power supply plane layer 133 is connected with a connecting means135. Thus, the electrostatic capacity between the separated power supplyplane layer 131 and the ground plane layer 132 increases.

In a laminated printed circuit board disclosed as Japanese PatentLaid-Open Publication No. 07-111387, as shown in FIG. 24, a power supplylayer 141 and a ground layer 142 are laminated. A slit 143 is diagonallyformed on a conductor of at least one of the power supply layer 141 andthe ground layer 142.

In a printed circuit board 150 disclosed as Japanese Patent Laid-OpenPublication No. 09-205290, as shown in FIG. 25, a power supply layer 151and a ground layer 152 are disposed on a first surface and a secondsurface of the printed circuit board 150. At a peripheral portion of thefirst surface, fine conductor patterns 154 and 155 are alternatelyformed. At a peripheral portion of the second surface, fine conductorpatterns 153 and 156 are alternately formed. The conductor patterns 154are connected to the ground layer 152. The conductor patterns 155 areconnected to the power supply layer 151. The conductor patterns 153opposite to the conductor patterns 154 are connected to the power supplylayer 151. The conductor patterns 156 opposite to the conductor patterns155 are connected to the ground layer 152.

In a printed circuit board disclosed as Japanese Patent Laid-Openpublication No. 09-283974, as shown in FIG. 26, a power supply layer 162and a first ground layer 163 are oppositely disposed with a dielectriclayer 166 and thereby a capacitor C1 is formed. A power supply layer 162and a second ground layer 164 are oppositely disposed with a dielectriclayer 167 and thereby a capacitor C2 is formed. In addition, the firstground layer 163 and the second ground layer 165 are connected through aresistor layer 166.

However, in the cage structure of the printed circuit board shown inFIG. 20, the printed board 101 and the cage 107 function as shields.Thus, when a substrate or a nonconductive cage made of plastic is used,it does not function as a shield. In this case, the cage structurecannot suppress an electromagnetic wave from radiating. In the IC card111 shown in FIG. 21 and the liquid crystal displaying device shown inFIG. 22, since the printed circuit board requires a metal panel, themounting density decreases and the fabrication cost increases.

In the printed circuit boards shown in FIGS. 23, 24, 25, and 26, theythat are radiation sources suppress undesired electromagnetic waves fromradiating. In these printed circuit boards, the voltage fluctuationbetween the ground for supplying a reference voltage and the powersupply layer for supplying a power supply voltage is suppressed.However, in the printed circuit board 130 shown in FIG. 23, even if thepower supply plane layer and part of the ground plane layer areadjacently disposed, the increase of the resultant electrostaticcapacitance is very small. Thus, the fluctuation of the power supplyvoltage cannot be sufficiently suppressed. In the printed circuit board140 shown in FIG. 24, since the slit 143 formed on the power supplylayer 141 or/and the ground layer 142 function as slot antennas, theradiation of the electromagnetic waves further increases.

In the printed circuit board 150 shown in FIG. 25, since the polarity ofthe voltage generated between the conductor patterns 154 and 153 isreverse from the polarity of the voltage generated between the conductorpatterns 155 and 156 adjacent to the conductor patterns 154 and 153, thevoltages at the end portions of the printed circuit board are offset soas to suppress an electromagnetic wave from radiating. However, sincethe voltage fluctuation between the power supply layer 151 and theground layer 152 still takes place, undesired electromagnetic wavesradiated from the power supply layer 151 and the ground layer 152 cannotbe suppressed. In the laminated printed circuit board 161 shown in FIG.26, although the radiation of undesired electromagnetic waves and themalfunction of device due to the voltage fluctuation between the powersupply and the ground are suppressed, another ground layer 164 and asecond dielectric layer 167 should be additionally disposed along withthe ground layer 163. Thus, the structure becomes complicated and thecost increases.

In the above-descried related art references, the structures of theprinted circuit boards should be largely modified. Thus, to apply thetechnologies of the above-described related art references to printedcircuit boards that are provided as products, they should be redesignedfrom the beginning.

The present invention is made from the above-described point of view. Anobject of the present invention is to provide a laminated printedcircuit board that suppresses the voltage between a power supply and aground from fluctuating and effectively suppresses an undesiredelectromagnetic wave from radiating without need to largely modify acircuit layout of a conventional printed circuit board.

SUMMARY OF THE INVENTION

A first aspect of the present invention is a printed circuit boardhaving a metal layer, a dielectric layer, a ground layer, and a powersupply layer, the metal layer and the dielectric layer being alternatelylaminated, the ground layer supplying a reference voltage, the powersupply layer supplying a power supply voltage, the ground layer and thepower supply layer being disposed as inner layers, comprising at leasttwo belt-shaped planes formed on periphery of at least one of twosurfaces of the layers of the printed circuit board, a plurality ofviaholes for causing each of the belt-shaped planes to be connected tothe ground layer and the power supply layer so that the voltages of thebelt-shaped planes become the same, and a plurality of capacitorsconnected between the belt-shaped planes.

A plurality of capacitor resistor series circuits are disposed betweenthe belt-shaped conductive loops.

A second aspect of the present invention is a printed circuit boardhaving a metal layer, a dielectric layer, a ground layer, and a powersupply layer, the metal layer and the dielectric layer being alternatelylaminated, the ground layer supplying a reference voltage, the powersupply layer supplying a power supply voltage, the ground layer and thepower supply layer being disposed as inner layers, comprising aplurality of conductor patterns formed at a part of or on the entireperiphery of at least one of two surfaces of the layers of the printedcircuit board, a plurality of viaholes for causing the conductorpatterns to be alternately connected to the ground layer and the powersupply layer, and a plurality of capacitors, disposed on the frontsurface of the conductor patterns, for connecting adjacent patterns ofthe conductor patterns.

A third aspect of the present invention is a printed circuit boardhaving a metal layer, a dielectric layer, a ground layer, and a powersupply layer, the metal layer and the dielectric layer being alternatelylaminated, the ground layer supplying a reference voltage, the powersupply layer supplying a power supply voltage, the ground layer and thepower supply layer being disposed as inner layers, comprising aplurality of conductor patterns formed at a part or on the entireperiphery of at least one of two surfaces of the layers of the printedcircuit board, a plurality of viaholes for causing the conductorpatterns to be alternately connected to the ground layer and the powersupply layer, and a plurality of capacitor resistor series circuits,disposed on the front surface of the conductor patterns, for connectingadjacent patterns of the conductor patterns.

A fourth aspect of the present invention is a printed circuit boardhaving a metal layer, a dielectric layer, a ground layer, and a powersupply layer, the metal layer and the dielectric layer being alternatelylaminated, the ground layer supplying a reference voltage, the powersupply layer supplying a power supply voltage, the ground layer and thepower supply layer being disposed as inner layers, comprising aplurality of pairs of pads connected to the power supply layer and theground layer through viaholes on the periphery of the front surface ofthe printed circuit board or on the periphery of the power supply layer,and a plurality of resistor capacitor series circuits disposed betweeneach pair of the pads, wherein the value of the resistor is set so thatthe value of parallel resistors on each side of the printed circuitboard is equal to the characteristic impedance value assuming that thepower supply layer and the ground layer are treated as parallel platelines, the relevant sides being terminated.

Thus, according to a laminated printed circuit board of the presentinvention, at each end portion of the board, where the voltage between aground layer and a power supply layer becomes maximum, a decouplingcircuit that controls a resonance frequency and a circuit that has anelectric loss are disposed. Thus, an undesired electromagnetic wave canbe effectively suppressed without need to largely modify the structureof a conventional printed circuit board and the layout of circuitsthereon.

These and other objects, features and advantages of the presentinvention will become more apparent in light of the following detaileddescription of a best mode embodiment thereof, as illustrated in theaccompanying drawings

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is an exploded perspective view showing the structure of alaminated printed circuit board according to a first embodiment of thepresent invention;

FIG. 2 is a sectional view taken along line A-A′ shown in FIG. 1;

FIG. 3 is a perspective view showing the structure of a conventionallaminated printed circuit board;

FIG. 4 is an equivalent circuit diagram showing a power supply systemcomposed of a power supply plane and a ground plane of the conventionallaminated printed circuit board shown in FIG. 3;

FIG. 5 is a graph showing a frequency characteristic of impedance of adecoupling circuit;

FIG. 6 is a graph showing a radiation characteristic of an undesiredelectromagnetic wave radiated from the printed circuit board accordingto the first embodiment of the present invention;

FIG. 7 is an exploded perspective view showing the structure of alaminated printed circuit board according to a second embodiment of thepresent invention;

FIG. 8 is a sectional view taken along line A-A′ shown in FIG. 7;

FIG. 9 is a graph showing a radiation characteristic of an undesiredelectromagnetic wave radiated from the printed circuit board accordingto the second embodiment of the present invention;

FIG. 10 is an exploded perspective view showing the structure of alaminated printed circuit board according to a third embodiment of thepresent invention;

FIG. 11 is a sectional view taken along line A-A′ shown in FIG. 10;

FIG. 12 is an exploded perspective view showing the structure of alaminated printed circuit board according to a fourth embodiment of thepresent invention;

FIG. 13 is a sectional view taken along line A-A′ shown in FIG. 12;

FIG. 14 is an exploded perspective view showing the structure of alaminated printed circuit board according to a fifth embodiment of thepresent invention;

FIG. 15 is a sectional view taken along line A-A′ shown in FIG. 14;

FIG. 16 is an equivalent circuit diagram showing the theory according tothe fifth embodiment of the present invention;

FIG. 17 is a perspective view showing the structure of the laminatedprinted circuit board according to the fifth embodiment of the presentinvention;

FIG. 18 is a graph showing an undesired electromagnetic wave suppressingeffect according to the fifth embodiment of the present invention;

FIG. 19 is a perspective view showing the structure of a laminatedprinted circuit board according to a modification of the fifthembodiment of the present invention;

FIG. 20 is a schematic diagram for explaining a printed circuit board inconsideration of suppressing an undesired electromagnetic wave fromradiating according to a related art reference;

FIG. 21 is a sectional view taken from line A-A′ shown in FIG. 20;

FIG. 22 is a sectional view showing the structure of another printedcircuit board in consideration of suppressing an undesiredelectromagnetic wave from radiating according to another related artreference;

FIG. 23 is an exploded sectional view showing the structure of anotherprinted circuit board in consideration of suppressing an undesiredelectromagnetic wave from radiating according to another related artreference;

FIG. 24A is a side view showing the structure of a printed circuit boardin consideration of suppressing an undesired electromagnetic wave fromradiating according to a related art reference;

FIG. 24B is a plan view of FIG. 24A;

FIG. 25 is a partial sectional view showing the structure of anotherprinted circuit board in consideration of suppressing an undesiredelectromagnetic wave from radiating according to another related artreference; and

FIG. 26 is a vertical sectional view showing the structure of a printedcircuit board in consideration of suppressing an undesiredelectromagnetic wave from radiation according to another related artreference.

DESCRIPTION OF PREFERRED EMBODIMENTS

Next, with reference to the accompanying drawings, embodiments of thepresent invention will be described. FIGS. 1 and 2 show the structure ofa laminated printed circuit board 1 according to a first embodiment ofthe present invention. FIG. 1 is an exploded perspective view showingthe structure of individual layers of the printed circuit board 1. FIG.2 is a sectional view taken along the line A-A′ shown in FIG. 1.

The printed circuit board 1 has four metal layers on which circuitpatterns are formed by electrolytic plating method. Each layer isseparated with an insulator (not shown) composed of such as glass epoxyor paper phenol. The four layers of the printed circuit board 1 arereferred to as a first layer, a second layer, a third layer, and afourth layer that are successively disposed from the top thereof. Thefirst layer and the fourth layer are used as signal wiring layers 4 aand 4 b for wiring signal lines. The second layer is a ground layer 2.The third layer is a power supply layer 3. So-called solid patterns areformed on the entire surfaces of the ground layer 2 and the power supplylayer 3.

The first layer 4 a that is the top layer has two patterns 5 and 6 thatform belt-shaped conductive patterns such as conductive loops on theperiphery of the printed circuit board. The patterns 5 and 6 areconnected to the power supply layer 3 and the ground layer 2 throughviaholes formed at predetermined intervals, respectively. The patternconnected to the power supply layer 3 is referred to as top layer powersupply pattern 6. The pattern connected to the ground layer is referredto as top layer ground pattern 5. Capacitors 8 are disposed atpredetermined intervals between the top layer power supply pattern 6 andthe top layer ground pattern 5 at predetermined intervals. The intervalsof the viaholes that connect the inner patterns of the power supplylayer 3 and the ground layer 2 and the top layer power supply pattern 6and the top layer ground pattern 5 are preferably as small as possible.The maximum interval of adjacent viaholes 7 is preferably equal to orless than ½ of the wave length in the printed circuit board, the wavelength being equivalent to the upper limit frequency in a frequencyregion for suppressing an undesired electromagnetic wave from radiating.This is because assuming that the power supply layer 3 and the top layerpower supply pattern 6 or the ground layer 2 and the top layer groundpattern 5 are considered as transmission lines, at a frequency of whichthe interval of adjacent viaholes is ½ wave length, a resonance takesplace due to a short circuit at both ends. Thus, an undesiredelectromagnetic wave in high level should be prevented from radiating.Assuming that the target frequency is in the range from 30 MHz to 1000MHz as defined by VCCI (Voluntary Control Council for Interference byInformation Technology Equipment) and that a printed circuit boardcomposed of glass epoxy with a specific inductive capacity of around 5is used, the maximum interval of adjacent viaholes becomes equal to orless than ½ of the wave length of the printed circuit board at the upperlimit frequency of 1000 MHz. Thus, the maximum interval becomes around67 mm or less.

Likewise, the interval of each capacitor 8 disposed between the toplayer power supply pattern 6 and the top layer ground pattern 5 ispreferably equal to or smaller than ½ of the wave length in the printedcircuit board, the wave length being equivalent to the upper limitfrequency in the frequency range, so as to suppress an undesiredelectromagnetic wave from radiating.

Next, with reference to the accompanying drawings, a mechanism forsuppressing an undesired electromagnetic wave from radiating in theprinted circuit board according to the first embodiment of the presentinvention will be described.

FIG. 3 shows the structure of a conventional printed circuit board 11.As described above, when a switching operation is performed in theprinted circuit board that is a main radiation source, the power supplyvoltage fluctuates between a power supply layer and a ground layer. Inthe conventional printed circuit board 11 shown in FIG. 3, a powersupply system composed of a power supply layer 13 and a ground layer 12can be expressed as an equivalent circuit shown in FIG. 4 in such amanner that a decoupling circuit 14 is added to parallel plate lines 20composed of the power supply layer 13 and the ground layer 12. Thedecoupling circuit 14 corresponds to a decoupling capacitor 15 disposedin the vicinity of a switching device such as an IC 18 or an oscillator19. The decoupling circuit 14 can be expressed as a series circuitcomposed of a capacitance 16 of a capacitor and a parasitic inductancecomponent 17 that resides in the capacitance 15, a viahole, a pad, andthe like.

In the case that the decoupling circuit 14 operates as only thecapacitance component 16, when a capacitor with sufficient capacitanceis selected, the power supply voltage can be suppressed fromfluctuating. However, in a real decoupling circuit, the parasiticinductance component 17 exists and it cannot be removed. FIG. 5 shows afrequency characteristic of impedance of a decoupling circuit havingcapacitors with different capacitance values and with parasiticinductance of 30 nH (refer to “Technical Report on PracticallySuppressing Noise (translated title)” written by H. W. OTT, supervisedby Deguchi, Jatech Shuppan, p. 313). In a frequency band higher than aresonance frequency, the impedance at both ends of the decouplingcircuit becomes high due to an influence of parasitic inductance.

In the equivalent circuit shown in FIG. 4, the fluctuation of the powersupply voltage due to a switching operation of an IC travels as a waveon the parallel plate lines. The wave reflects at each end as an opencircuit. The reflected wave also reflects at the other end. The multiplereflections cause the parallel plate lines 20 to resonate at apredetermined frequency. The resonance results in radiating an undesiredelectromagnetic wave in high level. The resonance frequency depends on acharacteristic impedance. The characteristic impedance depends on theconstant of the decoupling circuit 14 and the size and structure of thetransmission line. It is assumed that as shown in FIG. 3, each of thefour layers of 100 (W) mm×160 (L) mm has one oscillator and one IC, eachof which is connected to a 0.1 Ω decoupling capacitor. At this point, anundesired electromagnetic wave radiated from the power supply systemcomposed of the power supply layer and the ground layer resonates ataround 170 MHz and 480 MHz as denoted by peaks of a dotted curve shownin FIG. 6. In this frequency band, the resonance characteristic of thepower supply system depends on the inductance component of thedecoupling circuit. When the inductance component is decreased, theimpedance between the power supply layer and the ground layer isdecreased. Thus, an undesired electromagnetic wave radiated from thepower supply system can be suppressed.

The parasitic inductance of the decoupling circuit can be decreased withthe same decoupling circuit connected in parallel thereto. When ndecoupling circuits with parasitic inductance L each are connected inparallel, the total inductance can be decreased to L/n. In other words,the parasitic inductance can be decreased by connecting the power supplylayer and the ground layer with a plurality of viaholes and capacitorsas with the printed circuit board 1 shown in FIG. 1. When this structureis formed at end portions of the printed circuit board, where that theend portions are treated as open ends assuming that the power supplylayer and the ground layer that are parallel plate lines, a remarkableeffect can be obtained.

In the printed circuit board 1 shown in FIG. 1, at each end portionthereof, the top layer power supply pattern 6 and the top layer groundpattern 5 are formed and connected to the power supply layer 3 and theground layer 2 through three viaholes each, respectively. A radiationcharacteristic of an undesired electromagnetic wave of which both thepatterns are connected with three 0.1 Ω capacitors is denoted by a solidcurve shown in FIG. 6. This is a radiation characteristic of anundesired electromagnetic wave radiated from the printed circuit boarddue to the multiple reflections. In particular, at frequencies of 170MHz and 480 MHz, the radiation of the undesired electromagnetic wave canbe remarkably decreased.

As described above, to decrease the high frequency impedance between thepower supply layer 3 and the ground layer 2, each capacitor 8 and eachviahole 7 that connects the ground layer 2 and the power supply layer 3to the top layer ground pattern 5 and the top layer power supply pattern6 should be adjacently disposed with the minimum distance so as tominimize the influence of the parasitic inductance.

FIGS. 7 and 8 show the structure of a laminated printed circuit board 21according to a second embodiment of the present invention. FIG. 7 is anexploded perspective view showing the printed circuit board 21. FIG. 8is a sectional view taken along line A A′ shown in FIG. 7.

The printed circuit board 21 has four metal layers on which circuitpatterns are formed by electrolytic plating method. Each layer isseparated with an insulator composed of such as glass epoxy or paperphenol. The four layers of the printed circuit board 21 are referred toas a first layer, a second layer, a third layer, and a fourth layer thatare successively disposed from the top thereof. The first layer and thefourth layer are used as signal wiring layers 24 for wiring signallines. The second layer is a ground layer 22. The third layer is a powersupply layer 23. So-called solid patterns are formed on the entiresurfaces of the ground layer 22 and the power supply layer 23.

On the periphery of the printed circuit board, a top layer power supplypattern 26 and a top layer ground pattern 25 that compose belt-shapedconductive patterns such as conductive loops connected to the powersupply layer 23 and the ground layer 22 through a plurality of viaholes27 are formed. A plurality of capacitor 28 resistor 29 series circuitsare disposed at predetermined intervals between the top layer powersupply pattern 26 and the top layer ground pattern 25. The capacitor 28and the resistor 29 are connected through a pad 30 disposed between thetop layer power supply pattern 26 and the top layer ground pattern 25.

The intervals of the viaholes that connect the inner patterns of thepower supply layer 23 and the ground layer 22 and the top layer powersupply pattern 26 and the top layer ground pattern 25 are preferably assmall as possible. The maximum interval of adjacent viaholes 27 ispreferably equal to or less than ½ of the wave length in the printedcircuit board, the wave length being equivalent to the upper limitfrequency in a frequency region for suppressing an undesiredelectromagnetic wave from radiating. Likewise, the interval of thecapacitor 28 and the resistor 29 disposed between the top layer powersupply pattern 26 and the top layer ground pattern 25 is preferablyequal to or smaller than ½ of the wave length in the printed circuitboard, the wave length being equivalent to the upper limit frequency inthe frequency range, so as to suppress an undesired electromagnetic wavefrom radiating.

Next, a mechanism for suppressing an undesired electromagnetic wave fromradiating in the printed circuit board according to the secondembodiment of the present invention will be described.

As described above (see FIG. 4), since the parallel plate lines as thepower supply layer and the ground layer resonate, an electromagneticwave in high level radiates due to the fluctuation of the power supplyvoltage of the laminated printed circuit board. Thus, to suppress anundesired electromagnetic wave in high level from radiating, withresistors disposed on the lines 20, the resonance Q should be decreased.The resistors are preferably disposed at end portions as open circuitsof the lines. A solid curve shown in FIG. 9 represents a radiationcharacteristic of an undesired electromagnetic wave in the case that atop layer power supply pattern and a top layer ground pattern are formedat each end portion of the printed circuit board and connected to apower supply layer and a ground layer through three viaholes each,respectively, and that a series circuit of three 0.1 μ F capacitors andone 6 Ω resistor is disposed between these patterns. In comparison witha radiation (denoted by a dotted curve shown in FIG. 9) of theconventional printed circuit board, an undesired electromagnetic wave issuppressed in most frequency bands ranging from 30 MHz to 800 MHz. Sincethe serial circuit of the resistor and the capacitors is disposed ateach end portion of the printed circuit board, a DC current issuppressed from flowing between the power supply layer and the groundlayer.

As described above, to decrease the high frequency impedance between thepower supply layer 23 and the ground layer 22, each circuit of thecapacitor 28 and the resistor 29 and each viahole 27 that connects theground layer 22 and the power supply layer 23 to the top layer groundpattern 25 and the top layer power supply pattern 26 should beadjacently disposed with the minimum distance so as to minimize theinfluence of the parasitic inductance.

FIGS. 10 and 11 show the structure of a laminated printed circuit board31 according to a third embodiment of the present invention. FIG. 10 isan exploded perspective view of the printed circuit board 31. FIG. 11 isa sectional view taken along line A A′ shown in FIG. 10.

The printed circuit board 31 has four metal layers on which circuitpatterns are formed by electrolytic plating method. Each layer isseparated with an insulator composed of such as glass epoxy or paperphenol. The four layers of the printed circuit board 31 are referred toas a first layer, a second layer, a third layer, and a fourth layer thatare successively disposed from the top thereof. The first layer and thefourth layer are used as signal wiring layers 34 for wiring signallines. The second layer is a ground layer 32. The third layer is a powersupply layer 33. So-called solid patterns are formed on the entiresurfaces of the ground layer 32 and the power supply layer 33.

On the first layer 34 a as the top layer, a plurality of conductorpatterns 35 a and a plurality of conductor patterns 35 b are alternatelyformed on opposite end portions of the printed circuit board 31. Theconductor patterns 35 a are connected to the power supply layer 33through viaholes 36. The conductor patterns 35 b are connected to theground layer 32 through the viaholes 36. The adjacent conductor patterns35 a and 35 b are connected in high frequency through capacitors 37.

As the theory for suppressing an undesired electromagnetic wave fromradiating in a power supply system of the printed circuit board 31, aplurality of conductor patterns connected to the power supply layer 33and the ground layer 32 are formed. The conductor patterns are connectedwith the capacitors 37. Thus, the parasitic inductance can be decreased.Consequently, to decrease the parasitic inductance, each capacitor 37and each viahole 36 that connects the conductor patterns 35 a and 35 b,the power supply layer 33, and the ground layer 32 should be adjacentlydisposed.

FIGS. 12 and 13 show the structure of a laminated printed circuit board41 according to a forth embodiment of the present invention. FIG. 12 isan exploded perspective view of the printed circuit board 41. FIG. 13 isa sectional view taken along line A A′ shown in FIG. 12.

The printed circuit board 41 has four metal layers on which circuitpatterns are formed by electrolytic plating method. Each layer isseparated with an insulator composed of such as glass epoxy or paperphenol. The four layers of the printed circuit board 41 are referred toas a first layer, a second layer, a third layer, and a fourth layer thatare successively disposed from the top thereof. The first layer and thefourth layer are used as signal wiring layers 44 for wiring signallines. The second layer is a ground layer 42. The third layer is a powersupply layer 43. So-called solid patterns are formed on the entiresurfaces of the ground layer 42 and the power supply layer 43.

On the first layer 44 a as the top layer, a conductor pattern 45 a and aconductor pattern 45 b are alternately formed on opposite end portionsof the printed circuit board 41. The conductor pattern 45 a is connectedto the power supply layer 43 at a part or on the entire peripherythereof through viaholes 46. The conductor pattern 45 b is connected tothe ground layer 42 at a part or on the entire periphery thereof throughthe viaholes 46. The adjacent conductor patterns 45 a and 45 b areconnected in high frequency through a plurality of capacitor 47 resistor48 serial circuits. The capacitor 47 and the resistor 48 are connectedthrough a pad 49.

As the theory for suppressing an undesired electromagnetic wave fromradiating in a power supply system of the printed circuit board 41, theresistors 48 are connected between the conductor pattern 45 a connectedto the power supply layer 43 and the conductor pattern 45 b connected tothe ground layer 42 through the capacitors 47. Due to the loss of theresistors 48, assuming that the power supply layer and the ground layerare treated as transmission lines, the resonance Q can be decreased.When a plurality of conductor patterns 45 a and a plurality of conductorpatterns 45 b are formed, the parasitic inductance can be decreased.Thus, the effect for suppressing an undesired electromagnetic wave fromradiating is improved. Consequently, to decrease the parasiticinductance, each circuit of the capacitor 47 and the resistor 48 andeach viahole 46 that connects the conductor patterns 45 a and 45 b, thepower supply layer 43, and the ground layer 42 should be adjacentlydisposed.

FIGS. 14 and 15 show the structure of a printed circuit board 51according to a fifth embodiment of the present invention. FIG. 14 is anexploded perspective view of the printed circuit board 51. FIG. 15 is asectional view taken along line A-A′ shown in FIG. 14.

The printed circuit board 51 has four metal layers on which circuitpatterns are formed by electrolytic plating method. Each layer isseparated with an insulator composed of such as glass epoxy or paperphenol. The four layers of the printed circuit board 51 arc referred toas a first layer, a second layer, a third layer, and a fourth layer thatare successively disposed from the top thereof. The first layer and thefourth layer are used as signal wiring layers 54 a and 54 b for wiringsignal lines. The second layer is a ground layer 52. The third layer isa power supply layer 53. So-called solid patterns are formed on theentire surfaces of the ground layer 52 and the power supply layer 53.

On the signal wiring layer 54 a as the top layer, a plurality of pairsof pads 58 a and 58 b are disposed at opposite end portions of theprinted circuit board 51 or at end portions of the power supply layer53. The pairs of the pads 58 a and 58 b are connected to the powersupply layer 53 and the ground layer 52 through viaholes. A seriescircuit of resistor 56 and capacitor 55 is disposed between each pair ofpads 58 a and 58 b. The resistor 56 and the capacitor 57 are connectedwith a pad 58 c disposed between the pair of pads 58 a and 58 b. Theresistance of the resistor 56 is set so that the resistance value of theparallel resistors disposed on one side of the printed circuit board 51is equal to the characteristic impedance assuming that the power supplylayer 53 and the ground layer 52 are treated as parallel plate lines.

Next, a mechanism for suppressing an undesired electromagnetic wave fromradiating in the printed circuit board according to the fifth embodimentof the present invention will be described.

As described above, in the conventional printed circuit board 11 shownin FIG. 3, a power supply system composed of a power supply layer 13 anda ground layer 12 can be expressed as an equivalent circuit shown inFIG. 4 in such a manner that a decoupling circuit 14 is added toparallel plate lines 20 composed of the power supply layer 13 and theground layer 12. When a resonance takes place between the lines, thepower supply system radiates an undesired electromagnetic wave in veryhigh level. To suppress the resonance, as expressed with an equivalentcircuit shown in FIG. 16, the lines are terminated with a terminatingcircuit 62 with resistance R that is equal to characteristic impedanceZc of the lines assuming that the power supply layer 53 and the groundlayer 52 are treated as parallel plate lines 62. To prevent a DC currentfrom flowing between the power supply and the ground, the terminatingcircuit 62 may be composed of a capacitor 63 and resistor 64 seriescircuit .

FIG. 17 shows a four-layered printed circuit board 71 with a size of 115mm (W)×160 mm (L). The thickness between a power supply layer 73 and aground layer 72 is 1 mm. The printed circuit board 71 has an oscillator74, an IC 75, and a decoupling capacitor 76. FIG. 18 shows a resistancedependency of a terminating circuit against a radiation characteristicof an undesired electromagnetic wave radiated from the power supplysystem of the printed circuit board 71. At each end portion of theprinted circuit board 71, three terminating circuits 62 are disposed inparallel. The resistance values of the three terminating circuits 62 are10 Ω (parallel resistance value: 3.3 Ω), 5 Ω (parallel resistance value:1.7 Ω, and 1 Ω (parallel resistance value: 0.3 Ω). The capacitance valueof each capacitor is 0.1 μF. Assuming that the specific inductivecapacity is 4.8, the characteristic impedance of the parallel platelines composed of the power supply layer 73 and the ground layer 72 isaround 1.5 Ω. The radiation characteristic in the case that aterminating circuit is not disposed is denoted by a solid curve (a)shown in FIG. 18. The radiation characteristic in the case that aterminating circuit with a resistor of 10•is denoted by a curve (b)shown in FIG. 18. The radiation characteristic in the case that aterminating circuit with a resistor of 5•is denoted by a dashed curveshown in FIG. 18. The radiation characteristic in the case that aterminating circuit with a resistor of 1•is denoted by a dotted lineshown in FIG. 18. In the entire frequency bands, the radiation level inthe case that a terminating circuit with a resistor of 5•that is closeto the characteristic impedance Zc of the parallel plate lines is thelowest. When a terminating circuit with another resistor is used, theradiation level decreases in comparison with the case that noterminating circuit is used. However, in consideration of optimization,the impedance should be matched as a major factor.

In such a structure, to reduce the influence of parasitic inductance ofcapacitors, resistors, and viaholes, three terminating circuits aredisposed in parallel at each end portion of the printed circuit board.

Since the three terminating circuits are disposed in parallel at eachend portion of the printed circuit board, the influence of parasiticinductance of the capacitors, resistors, and viaholes can be reduced.

When the shape of a printed circuit board 81 is almost square as shownin FIG. 19, it is necessary to consider two traveling directions x and yof radio waves. In this case, terminating circuits having parallelresistance values that are equal to characteristic impedance values Zxand Zy of parallel plate lines in the traveling directions of radiowaves are disposed at end portions in the traveling directions of radiowaves.

When there are a plurality of power supply layers for supplyingdifferent voltages to circuits, the above-described terminating circuitsare disposed on each power supply plane.

Although the present invention has been shown and described with respectto a best mode embodiment thereof, it should be understood by thoseskilled in the art that the foregoing and various other changes,omissions, and additions in the form and detail thereof may be madetherein without departing from the spirit and scope of the presentinvention.

What is claimed is:
 1. A printed circuit board having at least onewiring layer, a dielectric layer, a ground layer, and a power supplylayer, the at least one wiring layer and the dielectric layer beingalternately laminated, the ground layer supplying a reference voltage,the power supply layer supplying a power supply voltage, the groundlayer and the power supply layer being disposed as inner layers,comprising: at least two separate conductive loops disposed along aperiphery of at least one of two surfaces of the layers of the printedcircuit board; a plurality of vias connecting each of said conductiveloops to one of the ground layer and the power supply layer; and aplurality of capacitors connected between said separate conductiveloops.
 2. The printed circuit board as set forth in claim 1, whereineach of the plurality of capacitors is connected in series with aresistor.
 3. The printed circuit board of claim 1, wherein one of theconductive loops is disposed entirely within another of the conductiveloops.
 4. The printed circuit board of claim 1, wherein the at least twoseparate conductive loops are disposed on a single plane.
 5. The printedcircuit board of claim 4, wherein said single plane is coplanar with oneof the at least one wiring layers.
 6. The printed circuit board of claim5, wherein one of the conductive loops is disposed entirely withinanother of the conductive loops.
 7. The printed circuit board of claim6, wherein each of the capacitors connected between adjacent saidconductive loops is arranged in series with a resistor.
 8. The printedcircuit board of claim 6, wherein there are no more than two saidconductive loops coplanar with each of said at least one wiring layer.9. The printed circuit board of claim 8, wherein each of the capacitorsconnected between adjacent said conductive loops is arranged in serieswith a resistor.
 10. A printed circuit board having at least one wiringlayer, a dielectric layer, a ground layer, and a power supply layer, theat least one wiring layer and the dielectric layer being alternatelylaminated, the ground layer supplying a reference voltage, the a powersupply layer supplying a power supply voltage, the ground layer and thepower supply layer being disposed as inner layers, comprising: at leastthree adjacent conductor patterns formed in a line along at least oneedge of at least one of the layers of the printed circuit board; and aplurality of vias connecting each of the conductor patterns to one ofthe ground layer and the power supply layer, each said line of conductorpatterns being arranged so that the via connections alternate betweenthe ground layer and the power supply layer in successive said conductorpatterns; wherein each of the conductor patterns within each said lineof conductor patterns is connected to each adjacent said conductorpattern by a capacitor.
 11. The printed circuit board of claim 10,wherein each of the conductor patterns within each said line ofconductor patterns is connected to each adjacent said conductor patternby a series arrangement of a resistor and the capacitor.
 12. The printedcircuit board of claim 11, wherein at least one said line of conductorpatterns is disposed along substantially an entire said edge of theprinted circuit board.
 13. The printed circuit board of claim 12,wherein each of the conductor patterns is connected to one of the groundplane and the power supply plane by a plurality of said vias.
 14. Theprinted circuit board of claim 10, wherein at least one said line ofconductor patterns is disposed along substantially an entire said edgeof the printed circuit board.
 15. The printed circuit board of claim 14,wherein each of the conductor patterns is connected to one of the groundplane and the power supply plane by a plurality of said vias.
 16. Aprinted circuit board having at least one wiring layer, a dielectriclayer, a ground layer, and a power supply layer, the at least one wiringlayer and the dielectric layer being alternately laminated, the groundlayer supplying a reference voltage, the power supply layer supplying apower supply voltage, the ground layer and the power supply layer beingdisposed as inner layers, comprising: at least two separate belt-shapedconductive patterns disposed along a periphery of at least one of twosurfaces of the layers of the printed circuit board; a plurality of viasconnecting each of said separate belt-shaped conductive patterns to oneof the ground layer and the power supply layer; and a plurality ofcapacitors connected between said separate belt-shaped conductivepatterns.
 17. The printed circuit board as set forth in claim 16,wherein each of the plurality of capacitors is connected in series witha resistor.
 18. The printed circuit board as set forth in claim 16,wherein the at least two separate belt-shaped conductive patterns aredisposed on a single plane.
 19. The printed circuit board as set forthin claim 18, wherein said single plane is coplanar with one of the atleast one wiring layers.